In the related art, a semiconductor storage device such as a static random access memory (SRAM) is used to hold data in an information processing system. The semiconductor storage device includes, for example, a plurality of memory cells and a control circuit. In addition, each of the memory cells is connected to a word line and a pair of bit lines. Also, each of the memory cells is provided with a transistor that has a gate and a source connected to the word line and the bit lines and a storage element. A control circuit controls the word line of a memory cell, which is a destination of writing, such that it is brought to a high level (a power source potential VDD or the like) and controls the other word lines such that they are brought to a low level (reference potential VSS or the like). In addition, the control circuit controls one of the pair of bit lines such that it is brought to a high level (the VDD or the like) and controls the other such that it is brought to a low level (the VSS or the like) on the basis of a value of data to be written. Through the control, the transistor in the memory cell, which is the destination of writing, is shifted to an ON state, and data is written in the storage element.
In a system using the semiconductor storage device with the aforementioned configuration, there is concern that a data writing operation may become unstable if the power source potential VDD is caused to drop for the purpose of reducing power consumption. For example, a voltage between the gate and the source of the transistor may drop due to a drop of the power source potential VDD, and the transistor, which is to be brought into an ON state, may remain in an OFF state. Thus, a semiconductor storage device that relatively increases the voltage between the gate and the source of the transistor by setting the potential of a bit line connected to the source of the transistor to be lower than the reference potential VSS has been proposed (see Patent Literature 1, for example).